The present application relates to semiconductor devices, and particularly to power semiconductor devices which use intentionally introduced electrostatic charge in trenches which adjoin regions where current flows in the ON state.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel resistance and the drift region resistances which include the substrate resistance, spreading resistance and the epitaxial (epi) layer resistance.
Recently, the so called super-junction structure has been developed to reduce the drift region resistance. The super-junction structure consists of alternating highly doped p-type and n-type pillars or layers. For a given breakdown voltage, the doping concentrations of n-type pillar (the n-type drift region) can be one order of magnitude higher than that of conventional drift region provided that the total charge of n-type pillar is designed to be balanced with charge in the p-type pillar. In order to fully realize the benefits of the super-junction, it is desirable to increase the packing density of the pillars to achieve a lower RSP. However, the minimum pillar widths that can be attained in practical device manufacturing set a limitation on the reducing the cell pitch and scaling the device.
Recently, an invention (US application 20080164518), as shown in FIG. 1, has been disclosed to address this issue by incorporating fixed or permanent positive charge (QF) to balance the charge of p-type pillar. The permanent charge can also form an electron drift region in a power MOSFET by forming an inversion layer along the interface between the oxide and P Epi layer. By making use of this new concept, the area scaling limitation due to inter-diffusion of p-type pillar and n-type pillar can be eliminated. Consequently, a small cell pitch and high packing density of pillars as well the channel can be realize to reduce the device total on-resistance (and specific on-resistance RSP). In addition, the structure of FIG. 1 has a key advantage over conventional super-junction devices in that there is no JFET effect to limit the current so smaller cell pitches are highly desirable. Other embodiments of the same concept are shown in FIG. 2 where a planar gate is used and in FIGS. 3(a), (b) and (c) where a lateral device is shown.
One problem with super-junction devices generally, and specifically with the prior art devices shown in FIGS. 1-3(c), is the sensitivity to charge imbalance. If the total charge in an n-type pillar differs from the total charge in a p-type pillar, the maximum breakdown voltage achievable is reduced. For the device shown in FIG. 1, this imbalance is between the p-type pillar charge and the permanent charge (QF) in the dielectric material filling the trench.
In the MOSFET structures shown in FIGS. 1-3(c), the breakdown voltage is proportional to the trench depth, and the specific on-resistance RSP is proportional to the cell pitch. A small cell pitch or high aspect ratio of the trench (depth/width ratio) are desired to reduce the device total on-resistance and specific on-resistance RSP. As shown in FIG. 4, the minimum Cesium implant tilt angle φ that can be used determines the trench's highest possible aspect ratio (depth over width). As the trench depth increases and cell pitch reduces, the implant tilt angle φ becomes very small, which creates manufacturing problems. For example, for a trench with an aspect ratio of 15, an implant tilt angle φ of only about 3.8 degrees will be required. (An implant directly normal to the surface would be referred to as a zero tilt angle; typically the wafer is rotated during implantation, so that the effective implant angle is the same for any direction within the surface plane of the wafer.)
One way to improve the process window or the sensitivity of the breakdown voltage to charge imbalance for both conventional super-junction devices is to increase the width of the pillars or mesas of the prior art devices shown in FIGS. 1-3(c). FIG. 5 shows results from two-dimensional device simulations of the structure shown in FIG. 1 where the mesa width and trench widths are increased from 4 μm to 6 μm, resulting in devices with cell pitch of 8 μm and 12 μm respectively. For the target breakdown voltage of 600V, the process window is clearly improved by using the larger cell pitch of 12 μm compared to 8 μm. However, a clear disadvantage of increasing the cell pitch further is the reduction of specific-on resistance.
It is therefore desirable to reduce specific on-resistance RSP AND meet the required breakdown voltage with adequately large process window. To reduce specific on-resistance RSP a high aspect ratio of the trench is required. It is also necessary to balance the lowest RSP achievable against the manufacturability of the device.